1. Field of the Invention
The present invention relates to a compound semiconductor device and a method of manufacturing the same and, more particularly, to a field effect transistor having a multilevel recess structure and a method of manufacturing the same.
2. Description of the Prior Art
When an LDD structure is to be realized with an HJFET in order to attain a higher gate breakdown voltage, a lower source resistance, and suppression of the short channel effect and the surface effect, a multilevel recess structure must be formed by performing recess etching in two stages upon two alignment processes in a conventional case. In Japanese Unexamined Patent Publication No. 4-137737, a multilayered mask is used to selectively side-etch the mask, thereby realizing a two-level recess structure with improved controllability in the lateral direction.
When a two-level recess is formed using two alignment processes, misalignment disadvantageously occurs, and the distance between the gate and the n.sup.+ region is difficult to control and shorten. Even if the controllability in the lateral direction is improved using a multilayered mask, as disclosed in Japanese Unexamined Patent Publication No. 4-137737, etching also progresses along the lateral direction in recess etching, and a short gate and control of the recess width cannot be attained.
As for the direction of depth in recess etching, the recess depths at the first and second levels are controlled in terms of time, resulting in poor reproducibility, low controllability, and low uniformity.